That’s not true at all. It’s a common misconception but there’s nothing stopping x86 from also targeting a power efficient design. It’s all about architecture and not the instruction set. There just hasn’t been an incentive for Intel and AMD to focus their architectures on power efficiency since they make much more money in the server space. Lunar Lake is Intel’s first real attempt at it.
The Z1 Extreme has already shown very comparable and sometimes better performance and power efficiency as the M2 chips and the Lunar Lake chips trade blows with the X Elite not just in performance but also power draw.
If you wanna know more, this goes very in depth on what the differences are: https://chipsandcheese.com/p/why-x86-doesnt-need-to-die
Both RISC and CISC decode into micro-ops regardless. Read the article, it goes into detail, the diagrams make it pretty clear if you don’t want to read the whole article. Modern processors have no notable differences between RISC or CISC designs anymore in the way you described. The only thing RISC and CISC differs in is essentially just the interface that assemblers assemble code into. Which is different across ISAs anyways.